The present disclosure relates generally to performance counters, and more specifically, to accuracy sensitive performance counters.
Hardware counters, in computers, are registers built into microprocessors to store the counts of hardware-related activities within a computing system. Counters are sometimes used to conduct low-level performance analysis or tuning of the computer system.
In hardware performance analysis, retaining wide ranges of cycle accurate information is expensive for hardware to implement in terms of chip area and power. Proper sizing of these counters is problematic as chained sequences of events can produce unexpected overflow conditions which can be difficult to plan and predict in all situations. These overflow events result in the loss of data that can prevent analysis and understanding of underlying issues. Typically, this results in over-engineered solutions for contingency at the cost of more area and power, and at the same time, less information being collected as trade-offs are made between which information is most useful to collect given a limited number counters to contain said information.